HD64F2149YV datasheet(122/1075 Pages) RENESAS

122 / 1075 page

Section 4 Exception Handling

Rev. 3.00 Jan 18, 2006 page 94 of 1044

REJ09B0280-0300

4.2

Reset

4.2.1

Overview

A reset has the highest exception priority.

When the

RES pin goes low, all processing halts and the MCU enters the reset state. A reset

initializes the internal state of the CPU and the registers of on-chip supporting modules.

Immediately after a reset, interrupt control mode 0 is set.

Reset exception handling begins when the

RES pin changes from low to high.

The MCU can also be reset by overflow of the watchdog timer. For details, see section 14,

Watchdog Timer (WDT).

4.2.2

Reset Sequence

The MCU enters the reset state when the

RES pin goes low.

To ensure that the chip is reset, hold the

RES pin low for at least 20 ms when powering on. To

reset the chip during operation, hold the

RES pin low for at least 20 states. For pin states in a reset,

see appendix D.1, Pin States in Each Processing State.

When the

RES pin goes high after being held low for the necessary time, the chip starts reset

exception handling as follows:

[1] The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, and the I bit is set to 1 in CCR.

[2] The reset exception vector address is read and transferred to the PC, and program execution

starts from the address indicated by the PC.

Figures 4.2 and 4.3 show examples of the reset sequence.

HD64F2149YV データシート(PDF) 122 Page - Renesas Technology Corp