HD64F2149YV datasheet(125/1075 Pages) RENESAS

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Section 4 Exception Handling

Rev. 3.00 Jan 18, 2006 page 97 of 1044

REJ09B0280-0300

4.3

Interrupts

Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0)

from 31 input pins (NMI,

IRQ7 to IRQ0, and KIN15 to KIN0, WUE7 to WUE0), and internal

sources in the on-chip supporting modules. Figure 4.4 shows the interrupt sources and the number

of interrupts of each type.

The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),

16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), data

transfer controller (DTC), A/D converter (ADC), host interface (HIF:XBS, LPC), keyboard buffer

controller (PS2), and I

2C bus interface. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The

interrupt controller has two interrupt control modes and can assign interrupts other than NMI and

address break to either three priority/mask levels to enable multiplexed interrupt control.

For details on interrupts, see section 5, Interrupt Controller.

Interrupts

External

interrupts

Internal

interrupts

NMI (1)

IRQ7 to IRQ0 (8)

WDT* (2)

FRT (7)

TMR (10)

SCI (12)

DTC (1)

ADC (1)

HIF:XBS(4), LPC(4)

PS2 (3)

IIC (3)

Other (1)

Numbers in parentheses are the numbers of interrupt sources.

* When the watchdog timer is used as an interval timer, it generates an interrupt

request at each counter overflow.

Note:

Figure 4.4 Interrupt Sources and Number of Interrupts

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