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SH7014 データシート(PDF) 64 Page - Renesas Technology Corp |
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SH7014 データシート(HTML) 64 Page - Renesas Technology Corp |
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64 / 754 page  2. CPU Rev.5.00 Sep. 27, 2007 Page 30 of 716 REJ09B0398-0500 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Table 2.9 Instruction Formats Instruction Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxx xxxx 15 0 ⎯ ⎯ NOP ⎯ nnnn: Direct register MOVT Rn n format xxxx xxxx xxxx nnnn 15 0 Control register or system register nnnn: Direct register STS MACH,Rn Control register or system register nnnn: Indirect pre- decrement register STC.L SR,@-Rn mmmm: Direct register Control register or system register LDC Rm,SR m format xxxx mmmm xxxx xxxx 15 0 mmmm: Indirect post-increment register Control register or system register LDC.L @Rm+,SR mmmm: Direct register ⎯ JMP @Rm mmmm: PC relative using Rm ⎯ BRAF Rm |
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