SH7014 datasheet(80/754 Pages) RENESAS

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2. CPU

Rev.5.00 Sep. 27, 2007 Page 46 of 716

REJ09B0398-0500

Instruction

Instruction Code

Operation

Exec.

Cycles

T Bit

STS.L

MACH,@–Rn

0100nnnn00000010

− 4 → Rn, MACH → (Rn)

⎯

STS.L

MACL,@–Rn

0100nnnn00010010

− 4 → Rn, MACL → (Rn)

⎯

STS.L

PR,@–Rn

0100nnnn00100010

− 4 → Rn, PR → (Rn)

⎯

TRAPA

#imm

11000011iiiiiiii

PC/SR

→ stack area, (imm)

→ PC

⎯

Note:

The number of execution cycles before the chip enters sleep mode: The execution cycles

shown in the table are minimums. The actual number of cycles may be increased when (1)

contention occurs between instruction fetches and data access, or (2) when the destination

→ register) and the register used by the next

instruction are the same.

2.5

Processing States

2.5.1

State Transitions

The CPU has four processing states: reset, exception processing, program execution and power-

down. Figure 2.6 shows the transitions between the states.

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