SH7014 datasheet(14/754 Pages) RENESAS

14 / 754 page

Rev.5.00 Sep. 27, 2007 Page xiv of xxxiv

REJ09B0398-0500

Item

Page

Revision (See Manual for Details)

12.5.7 Constraints on

DMAC Use

366

Description amended

• When using an external clock source for the synchronization

clock, update the TDR with the DMAC

, and then after

five system clocks or more elapse, input a transmit clock. If

a transmit clock is input in the first four system clocks after

the TDR is written, an error may occur (figure 12.22).

13.1.1 Features

367

Description amended

• High-speed conversion

⎯ Minimum conversion time:

2.9 µs per channel (for 28-MHz operation)

1.4

μs per channel during continuous conversion

13.4 Operation

378

Description amended

• In buffer operation, the previous conversion result is saved

in a buffer register at the end of a conversion for the

relevant channel.

• In simultaneous sampling operation, the analog input

voltages of two channels are sampled simultaneously then

converted in order.

• Software, a timer conversion start trigger (MTU) can be

selected as the conversion start condition.

13.4.7 Conversion

Start Modes

388

Description amended

In the low-power conversion mode, power is applied to the

analog circuitry simultaneous to the conversion start (ADST

set). When 200 cycles of the reference clock have elapsed,

conversion becomes possible for the analog circuit and the first

A/D conversion begins. When performing consecutive

conversions, the second and later conversions are executed in

20 cycles. Select the basic clock with the CKS bit of the

ADCSR. When the A/D conversion ends, ADST is cleared to 0

and the analog circuit power supply is automatically cut off.

Because the analog circuit is only active during the A/D

conversion operation period in this mode, current consumption

can be reduced.

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