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AD9520-2/PCBZ データシート(PDF) 53 Page - Analog Devices

部品番号 AD9520-2/PCBZ
部品情報  12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO
PDF  84 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9520-2/PCBZ データシート(HTML) 53 Page - Analog Devices

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AD9520-2
Rev. 0 | Page 53 of 84
Data Transfer Format
Send byte format—the send byte protocol is used to set up the register address for subsequent commands.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Slave Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Read byte format—the combined format of the send byte and the receive byte.
S
Slave
Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
I²C Serial Port Timing
SDA
SCL
S
Sr
P
S
tFALL
tSET; DAT
tLOW
tRISE
tHLD; STR
tHLD; DAT
tHIGH
tFALL
tSET; STR
tHLD; STR
tSPIKE
tSET; STP
tRISE
tIDLE
Figure 60. I²C Serial Port Timing
Table 42. I2C Timing Definitions
Parameter
Description
fI2C
I²C clock frequency
tIDLE
Bus idle time between stop and start conditions
tHLD; STR
Hold time for repeated start condition
tSET; STR
Setup time for repeated start condition
tSET; STP
Setup time for stop condition
tHLD; DAT
Hold time for data
tSET; DAT
Setup time for data
tLOW
Duration of SCL clock low
tHIGH
Duration of SCL clock high
tRISE
SCL/SDA rise time
tFALL
SCL/SDA fall time
tSPIKE
Voltage spike pulse width that must be suppressed by the input filter



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