 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
AD9520-2/PCBZ データシート(PDF) 64 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9520-2/PCBZ データシート(HTML) 64 Page - Analog Devices |
|
|
64 / 84 page  AD9520-2 Rev. 0 | Page 64 of 84 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 193 Divider 1 (PECL) Divider 1 low cycles Divider 1 high cycles 33 194 Divider 1 bypass Divider 1 ignore SYNC Divider 1 force high Divider 1 start high Divider 1 phase offset 00 195 Unused Unused Channel 1 power- down Channel 1 direct-to- output Disable Divider 1 DCC 00 196 Divider 2 (PECL) Divider 2 low cycles Divider 2 high cycles 11 197 Divider 2 bypass Divider 2 ignore SYNC Divider 2 force high Divider 2 start high Divider 2 phase offset 00 198 Unused Unused Channel 2 power- down Channel 2 direct-to- output Disable Divider 2 DCC 00 199 Divider 3 (PECL) Divider 3 low cycles Divider 3 high cycles 00 19A Divider 3 bypass Divider 3 ignore SYNC Divider 3 force high Divider 3 start high Divider 3 phase offset 00 19B Unused Unused Channel 3 power- down Channel 3 direct-to- output Disable Divider 3 DCC 00 19C to 1DF Unused 00 VCO Divider and CLK Input 1E0 VCO divider Unused Unused VCO divider 00 1E1 Input CLKs Unused Unused (default = 01b) Power - down clock input section Power- down VCO clock interface Power- down VCO and CLK Select VCO or CLK Bypass VCO divider 20 1E2 to 22A Unused 00 System 230 Power-down and SYNC Unused Disable power-on SYNC Power- down SYNC Power- down distribution reference Soft SYNC 00 231 Unused Unused 00 Update All Registers 232 IO_UPDATE Unused IO_UPDATE (self-clearing) 00 233 to 9FF Unused 00 EEPROM Buffer Segment A00 EEPROM Buffer Segment Register 1 0 EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1) 00 A01 EEPROM Buffer Segment Register 2 EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1) 00 A02 EEPROM Buffer Segment Register 3 EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1) 00 A03 EEPROM Buffer Segment Register 4 0 EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2) 02 A04 EEPROM Buffer Segment Register 5 EEPROM Buffer Segment Register 5 (default: Bits[15:8] of starting register address for Group 2) 00 |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
