データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD9520-2/PCBZ データシート(PDF) 76 Page - Analog Devices

部品番号 AD9520-2/PCBZ
部品情報  12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO
PDF  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9520-2/PCBZ データシート(HTML) 76 Page - Analog Devices

Back Button AD9520-2/PCBZ Datasheet HTML 72Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 73Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 74Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 75Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 76Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 77Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 78Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 79Page - Analog Devices AD9520-2/PCBZ Datasheet HTML 80Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 76 / 84 page
background image
AD9520-2
Rev. 0 | Page 76 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
0F6
[7:0]
OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0F7
[7:0]
OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0F8
[7:0]
OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0F9
[7:0]
OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0FA
[7:0]
OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0FB
[7:0]
OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0FC
[7]
CSDLD En OUT7 OUT7 is enabled only if CSDLD is high.
[7]
CSDLD Signal
OUT7 Enable Status
0
0
Not affected by CSDLD signal (default).
1
0
Asynchronous power-down.
1
1
Asynchronously enable OUT7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect
and set the enable LD pin comparator bit (0x01D[3]).
0FC
[6]
CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[5]
CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[4]
CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[3]
CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[2]
CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[1]
CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[0]
CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[3]
CSDLD En
OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[2]
CSDLD En
OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[1]
CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[0]
CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 55. LVPECL Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
Description
190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
190
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
191
[7]
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
191
[6]
Divider 0 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
191
[5]
Divider 0 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
191
[4]
Divider 0 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
191
[3:0]
Divider 0 phase offset
Phase offset (default: 0x0).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com