AD9520-2SLASHPCBZ datasheet(25/84 Pages) AD

25 / 84 page

AD9520-2

Rev. 0 | Page 25 of 84

–100

–110

–120

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–140

–150

–160

100

100M

10M

100k

10k

FREQUENCY (Hz)

Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @

250 MHz, Divide-by-4

–100

–160

–150

–140

–130

–120

–110

100M

10M

100k

10k

FREQUENCY (Hz)

Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @

2.212 GHz; PFD = 15.36 MHz; LBW = 66 kHz; LVPECL Output = 122.88 MHz

–80

–90

–100

–110

–120

–130

–140

–150

–160

100M

10M

100k

10k

FREQUENCY (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 569fs

Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2.177 GHz;

PFD = 120 kHz; LBW = 2.18 kHz; LVPECL Output = 155.52 MHz

100M

10M

100k

10k

FREQUENCY (Hz)

–120

–160

–150

–140

–130

Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)

@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

62pF

33pF

240nF

C12

220nF

BYPASS

CAPACITOR

FOR LDO

820Ω

390Ω

BYPASS

Figure 34. PLL Loop Filter Used for Clock Generation Plot (See Figure 31)

1.5nF

2.2nF

4.7µF

C12

220nF

BYPASS

CAPACITOR

FOR LDO

2.1kΩ

3kΩ

BYPASS

Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 32)

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