AD9520-2SLASHPCBZ datasheet(74/84 Pages) AD

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AD9520-2

Rev. 0 | Page 74 of 84

Reg.

Addr

(Hex) Bit(s) Name

Description

01D

[7]

Enable

Status_EEPROM

at STATUS pin

Enables the Status_EEPROM signal at the STATUS pin.

[7] = 0; the STATUS pin is controlled by the 0x017[7:2] selection.

[7] = 1; select the status_EEPROM signal at STATUS pin. This bit overrides 0x017[7:2] (default).

01D

[6]

Enable

XTAL OSC

Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input.

[6] = 0; crystal oscillator maintaining amplifier disabled (default).

[6] = 1; crystal oscillator maintaining amplifier enabled.

01D

[5]

Enable clock

doubler

Enable PLL reference input clock doubler.

[5] = 0; doubler disabled (default).

[5] = 1; doubler enabled.

01D

[4]

Disable PLL

status register

Disables the PLL status register readback.

[4] = 0; PLL status register enabled (default).

[4] = 1; PLL status register disabled. If this bit is set, Register 01F is not automatically updated.

01D

[3]

Enable LD pin

comparator

Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.

When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the

LD pin to determine if the PLL was previously in a locked state (see Figure 46). Otherwise, this can be used

with the REFMON and STATUS pins to monitor the voltage on the LD pin.

[3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover

controller treats this pin as true (high, default).

[3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked).

01D

[1]

Enable external

holdover

Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)

[1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default).

[1] = 1; external holdover mode, holdover controlled by SYNC pin.

01D

[0]

Enable

holdover

Enables the internally controlled holdover function.

[0] = 0; holdover disabled (default).

[0] = 1; holdover enabled.

01E

[4:3]

External zero

delay

feedback

channel

divider select

[4]

[3]

Select Which Channel Divider to Use in the External Zero-Delay Path

Select Channel Divider 0 (default).

Select Channel Divider 1.

Select Channel Divider 2.

Select Channel Divider 3

01E

[2]

Enable external

zero delay

Selects which zero delay mode to use.

[2] = 0; enables internal zero delay mode if 0x01E[1] = 1 (default).

[2] = 1; enables external zero delay mode if 0x01E[1] = 1.

01E

[1]

Enable zero

delay

Enables zero delay function.

[1] = 0; disables zero delay function (default).

[1] = 1; enables zero delay function.

01F

[6]

VCO calibration

finished

(read-only)

Readback register. Indicates the status of the VCO calibration.

[6] = 0; VCO calibration not finished.

[6] = 1; VCO calibration finished.

01F

[5]

Holdover active

(read-only)

Readback register. Indicates if the part is in the holdover state (see Figure 46). This is not the same as

holdover enabled.

[5] = 0; not in holdover.

[5] = 1; holdover state active.

01F

[4]

REF2 selected

(read-only)

Readback register. Indicates which PLL reference is selected as the input to the PLL.

[4] = 0; REF1 selected (or differential reference if in differential mode).

[4] = 1; REF2 selected.

01F

[3]

VCO frequency

> threshold

(read-only)

Readback register. Indicates if the VCO frequency is greater than the threshold (see Table 17, REF1, REF2, and

VCO frequency status monitor parameter).

[3] = 0; VCO frequency is less than the threshold.

[3] = 1; VCO frequency is greater than the threshold.

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