AD9231 datasheet(8/36 Pages) AD

部品番号	AD9231

部品情報	12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

PDF	36 Pages

Scroll/Zoom	100%

メーカー	AD [Analog Devices]

ホームページ	http://www.analog.com

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8 / 36 page

AD9231

Rev. 0 | Page 8 of 36

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

tSSYNC

SYNC to rising edge of CLK setup time

0.24

tHSYNC

SYNC to rising edge of CLK hold time

0.40

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

SCLK pulse width high

tLOW

SCLK pulse width low

tEN_SDIO

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

SYNC

CLK+

tSSYNC

tHSYNC

Figure 4. SYNC Input Timing Requirements

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