AD9231 datasheet(32/36 Pages) AD

32 / 36 page

AD9231

Rev. 0 | Page 32 of 36

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Comments

0x0E

BIST enable

Open

BIST

INIT

Open

BIST

enable

0x00

When Bit 0 is set,

the BIST function is

initiated

0x10

Offset adjust

(local)

8-bit device offset adjustment [7:0] (local)

Offset adjust in LSBs from +127 to −128 (twos complement format)

0x00

Device offset trim

0x14

Output mode

00 = 3.3 V CMOS

10 = 1.8 V CMOS

Output mux

enable

(interleaved)

Output

disable

(local)

Open

Output

invert

(local)

00 = offset binary

01 = twos

complement

10 = gray code

11 = offset binary

(local)

0x00

Configures the

outputs and the

format of the data

0x15

OUTPUT_ADJUST

3.3 V DCO

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

1.8 V DCO

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes (default)

11 = 4 stripes

3.3 V data

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

1.8 V data

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

11 = 4 stripes

0x22

Determines

CMOS output drive

strength properties

0x16

OUTPUT_PHASE

DCO

output

polarity

0 =

normal

1 =

inverted

(local)

Open

Input clock phase adjust [2:0]

(Value is number of input clock

cycles of phase delay)

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

0x00

On devices that

utilize global clock

divide, this register

determines which

phase of the divider

output is used to

supply the output

clock; internal

latching is

unaffected

0x17

OUTPUT_DELAY

Enable

DCO

delay

Open

Enable

data

delay

Open

DCO/Data delay[2:0]

000 = 0.56 ns

001 = 1.12 ns

010 = 1.68 ns

011 = 2.24 ns

100 = 2.80 ns

101 = 3.36 ns

110 = 3.92 ns

111 = 4.48 ns

0x00

This sets the fine

output delay of the

output clock but

does not change

internal timing

0x19

USER_PATT1_LSB

0x00

User-defined

pattern, 1 LSB

0x1A

USER_PATT1_MSB

B15

B14

B13

B12

B11

B10

0x00

User-defined

pattern, 1 MSB

0x1B

USER_PATT2_LSB

0x00

User-defined

pattern, 2 LSB

0x1C

USER_PATT2_MSB

B15

B14

B13

B12

B11

B10

0x00

User-defined

pattern, 2 MSB

0x24

BIST signature LSB

BIST signature [7:0]

0x00

Least significant

byte of BIST

signature, read only

0x2A

Features

Open

OR OE

(local)

0x01

Disable the OR pin

for the indexed

channel

0x2E

Output assign

Open

0 =

ADC A

1 =

ADC B

(local)

Ch A =

0x00

Ch B =

0x01

Assign an ADC to an

output channel

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