AD9231 datasheet(33/36 Pages) AD

33 / 36 page

AD9231

Rev. 0 | Page 33 of 36

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Comments

Digital Feature Control

0x100

Sync control

(global)

Open

Clock

divider

sync

only

Clock

divider

sync

enable

Master

sync

enable

0x01

0x101

USR2

Enable

OEB

Pin 47

(local)

Open

Enable

GCLK

detect

Run

GCLK

Open

Disable

SDIO

pull-

down

0x88

Enables internal

oscillator for clock

rates < 5 MHz

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Note, Interfacing to High Speed ADCs via SPI.

Sync Control (Register 0x100)

Bits[7:3]—Reserved

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit 0) and the

clock divider sync enable bit (Address 0x100, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse it

receives and to ignore the rest. The clock divider sync enable

bit (Address 0x100, Bit 1) resets after it syncs.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal

is enabled when Bit 1 and Bit 0 are high and the device is

operating in continuous sync mode as long as Bit 2 of the

sync control is low.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

USR2 (Register 0x101)

Bit 7—Enable OEB Pin 47

Normally set high, this bit allows Pin 47 to function as the

output enable. If it is set low, it disables Pin 47.

Bit 3—Enable GCLK Detect

Normally set high, this bit enables a circuit that detects encode

rates below about 5 MSPS. When a low encode rate is detected

an internal oscillator, GCLK, is enabled ensuring the proper

operation of several circuits. If set low the detector is disabled.

Bit 2—Run GCLK

This bit enables the GCLK oscillator. For some applications

with encode rates below 10 MSPS, it may be preferable to set

this bit high to supersede the GCLK detector.

Bit 0—Disable SDIO Pull-Down

This bit can be set high to disable the internal 30 kΩ pull-down

on the SDIO pin, which can be used to limit the loading when

many devices are connected to the SPI bus.

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