AD9231 datasheet(29/36 Pages) AD

29 / 36 page

AD9231

Rev. 0 | Page 29 of 36

HARDWARE INTERFACE

The pins described in Table 13 constitute the physical interface

between the programming device of the user and the serial port

of the AD9231. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

The SPI interface is flexible enough to be controlled by

either FPGAs or microcontrollers. One method for SPI

configuration is described in detail in the AN-812 Appli-

cation Note, Microcontroller-Based Serial Port Interface

(SPI) Boot Circuit.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD9231 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

SDIO/DCS and SCLK/DFS serve a dual function when the

SPI interface is not being used. When the pins are strapped to

DRVDD or ground during device power-on, they are associated

with a specific function. The Digital Outputs section describes

the strappable functions supported on the AD9231.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the

PDWN pin serve as standalone CMOS-compatible control

pins. When the device is powered up, it is assumed that the

user intends to use the pins as static control lines for the duty

cycle stabilizer, output data format, output enable, and power-

down feature control. In this mode, connect the CSB chip select

to DRVDD, which disables the serial port interface.

Table 14. Mode Selection

External

Voltage

Configuration

SDIO/DCS

DRVDD

Duty cycle stabilizer enabled

AGND(default)

Duty cycle stabilizer disabled

SCLK/DFS

DRVDD

Twos complement enabled

AGND (default)

Offset binary enabled

OEB

DRVDD

Outputs in high impedance

AGND (default)

Outputs enabled

PDWN

DRVDD

Chip in power-down or standby

AGND (default)

Normal operation

SPI ACCESSIBLE FEATURES

Table 15 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9231 part-specific features are described in

detail in Table 16.

Table 15. Features Accessible Using the SPI

Feature

Description

Mode

Allows the user to set either power-down mode

or standby mode

Clock

Allows the user to access the DCS via the SPI

Offset

Allows the user to digitally adjust the

converter offset

Test I/O

Allows the user to set test modes to have known

data on output bits

Output Mode

Allows the user to set up outputs

Output Phase

Allows the user to set the output clock polarity

Output Delay

Allows the user to vary the DCO delay

AD9231 データシート(PDF) 29 Page - Analog Devices

AD9231 データシート(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

データシートダウンロード

リンク URL

AD9231 データシート(PDF) 29 Page - Analog Devices

AD9231 データシート(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

データシート ダウンロード

リンク URL

データシートダウンロード