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ST7713 データシート(PDF) 21 Page - Sitronix Technology Co., Ltd. |
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ST7713 データシート(HTML) 21 Page - Sitronix Technology Co., Ltd. |
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21 / 159 page  ST7713 Ver 1.6 2008-05 21 8. Timing chart 8.1 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (8080-series MCU interface) Fig. 8.1.1 Parallel interface timing characteristics (8080-series MCU interface) Signal Symbol Parameter Min Max Unit Description TAST Address setup time 5 ns D/CX TAHT Address hold time (Write/Read) 10 ns - TCHW Chip select “H” pulse width 0 ns TCS Chip select setup time (Write) 20 ns TRCS Chip select setup time (Read ID) 20 ns TRCSFM Chip select setup time (Read FM) 20 ns TCSF Chip select wait time (Write/Read) 10 ns CSX TCSH Chip select hold time 20 ns -(3-transfer for one pixel) TWC Write cycle 66 ns TWRH Control pulse “H” duration 25 ns WRX TWRL Control pulse “L” duration 15 ns TRC Read cycle (ID) 160 ns TRDH Control pulse “H” duration (ID) 90 ns RDX (ID) TRDL Control pulse “L” duration (ID) 45 ns When read ID data TRCFM Read cycle (FM) 169 ns TRDHFM Control pulse “H” duration (FM) 90 ns RDX (FM) TRDLFM Control pulse “L” duration (FM) 45 ns When read from frame memory TDST Data setup time 15 ns TDHT Data hold time 15 ns TRAT Read access time (ID) 40 ns TRATFM Read access time (FM) 340 ns D[17:0] TODH Output disable time 20 80 ns For maximum CL=30pF For minimum CL=8pF Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 ℃ |
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