ADP1864AUJZ-R7 datasheet(37/75 Pages) AD

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ADSP-BF506F EZ-KIT Lite Evaluation System Manual

2-3

ADSP-BF506F EZ-KIT Lite Hardware Reference

is configurable over the 2-wire interface (TWI) signals. Refer to the

power-on-self test (POST) example in the ADSP-BF506F installation

directory of VisualDSP++ for information on how to set up the TWI

interface.

The core voltage and clock rate can be set up on the fly by the processor.

The input clock is 25 MHz. The default boot mode for the processor is

SPI flash boot. See “Boot Mode Select Switch (SW2)” for information on

how to change the default boot mode.

Programmable Flags

The processor has 35 general-purpose input/output (GPIO) signals spread

across three ports (PF, PG, and PH). The pins are multi-functional and

depend on the ADSP-BF506F processor setup. The following tables show

how the programmable flag pins are used on the EZ-KIT Lite.

• PF programmable flag pins – Table 2-1

PG programmable flag pins – Table 2-2

PH programmable flag pins – Table 2-3

Table 2-1. Port F Programmable Flag Connections

Processor Pin

Other Processor Function

EZ-KIT Lite Function

PF0

TSCLK0/UA0_RX_ALT/TMR6/

CUD0

Default: LED0

Land grid array, expansion interface II

PF1

RSCLK0/UA0_TX_ALT/TMR5/

CDG0

Default: LED1

Land grid array, expansion interface II

PF2

DT0PRI/PWM0_BH/PPI_D8/

CZM0

Default: LED2

Land grid array, expansion interface II

PF3

TFS0/PWM0_BL/PPI_D9/

CDG0

Default: PB0

Land grid array, expansion interface II

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