HCS12 datasheet(124/452 Pages) FREESCALE

124 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

124

Freescale Semiconductor

Operation:

If Z

+ (N

⊕ V) = 0, then (PC) + $0002 + Rel ⇒ PC

For signed two’s complement values

if (Accumulator)

> (Memory), then branch

Description:

BGT can be used to branch after comparing or subtracting signed two’s

complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA,

SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value

is greater than the value in M. After CBA or SBA, the branch occurs if the

value in B is greater than the value in A.

See 3.8 Relative Addressing Mode for details of branch execution.

BGT

Branch if Greater than Zero

BGT

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

BGT rel8

REL

2E rr

PPP/P(1)

1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program

fetch cycle if the branch is not taken.

PPP/P(1)

Branch

Complementary Branch

Test

Mnemonic

Opcode

Boolean

Test

Mnemonic

Opcode

Comment

r>m

BGT

+ (N ⊕ V) = 0

≤m

BLE

Signed

≥m

BGE

⊕ V = 0

r<m

BLT

Signed

r=m

BEQ

Z = 1

≠m

BNE

Signed

≤m

BLE

+ (N ⊕ V) = 1

r>m

BGT

Signed

r<m

BLT

⊕ V = 1

≥m

BGE

Signed

r>m

BHI

+ Z = 0

≤m

BLS

Unsigned

≥m

BHS/BCC

C = 0

r<m

BLO/BCS

Unsigned

r=m

BEQ

Z = 1

≠m

BNE

Unsigned

≤m

BLS

+ Z = 1

r>m

BHI

Unsigned

r<m

BLO/BCS

C = 1

≥m

BHS/BCC

Unsigned

Carry

BCS

C = 1

No Carry

BCC

Simple

Negative

BMI

N = 1

Plus

BPL

Simple

Overflow

BVS

V = 1

No Overflow

BVC

Simple

r=0

BEQ

Z = 1

≠0

BNE

Simple

Always

BRA

—

Never

BRN

Unconditional

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