MPC8572ECLPXATLD datasheet(33/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 9 shows the GMII transmit AC timing diagram.

Figure 9. GMII Transmit AC Timing Diagram

8.2.2.2

GMII Receive AC Timing Specifications

Table 27 provides the GMII receive AC timing specifications.

Figure 10 provides the AC test load for eTSEC.

Figure 10. eTSEC AC Test Load

Table 27. GMII Receive AC Timing Specifications

At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

RX_CLK clock period

tGRX

—8.0

—

RX_CLK duty cycle

tGRXH/tGRX

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tGRDVKH

2.0

—

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

tGRDXKH

0—

—

RX_CLK clock rise (20%-80%)

tGRXR

——

1.0

RX_CLK clock fall time (80%-20%)

tGRXF

——

1.0

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII

receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock

reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to

the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

GTX_CLK

TXD[7:0]

tGTKHDX

tGTX

tGTXH

tGTXR

tGTXF

tGTKHDV

TX_EN

TX_ER

Output

LVDD/2

RL = 50 Ω

Z0 = 50 Ω

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