MPC8572ECLPXATLD datasheet(16/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Input Clocks

4.2

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter

specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2

× t

CCB, and minimum clock low time is 2 × tCCB. There is

no minimum RTC frequency; RTC may be grounded if not needed.

4.3

eTSEC Gigabit Reference Clock Timing

Table 6 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for

the MPC8572E.

SYSCLK jitter

—

+/– 150

4, 5, 6

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies.Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and 60 kHz on

SYSCLK.

Table 6. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LVDD/TVDD of 3.3V ± 5% or 2.5V ± 5%

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

fG125

—125

—

MHz

—

EC_GTX_CLK125 cycle time

tG125

—8

—

EC_GTX_CLK125 rise and fall time

L/TVDD=2.5V

L/TVDD=3.3V

tG125R, tG125F

——

0.75

1.0

Table 5. SYSCLK AC Timing Specifications (continued)

At recommended operating conditions with OVDD of 3.3V ± 5%.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

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