MPC8572ECLPXATLD datasheet(5/140 Pages) FREESCALE

5 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

– Fast pattern database compilation and fast incremental updates

– 16000 patterns, each up to 128 bytes in length

– Patterns can be split into 256 sets, each of which can contain 16 subsets

— Stateful rule engine enables hardware execution of state-aware logic when a pattern is found

– Useful for contextual searches, multi-pattern signatures, or for performing additional checks

after a pattern is found

– Capable of capturing and utilizing data from the data stream (such as LENGTH field) and

using that information in subsequent pattern searches (for example, positive match only if

pattern is detected within the number of bytes specified in the LENGTH field)

– 8192 stateful rules

— Deflate engine

– Supports decompression of DEFLATE compression format including zlib and gzip

– Can work independently or in conjunction with the Pattern Matching Engine (that is

decompressed data can be passed directly to the Pattern Matching Engine without further

software involvement or memory copying)

•

Two Table Lookup Units (TLU)

— Hardware-based lookup engine offloads table searches from e500 cores

— Longest prefix match, exact match, chained hash, and flat data table formats

— Up to 32 tables, with each table up to 16M entries

— 32-, 64-, 96-, or 128-bit keys

•Two I2C controllers

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

•

Boot sequencer

— Optionally loads configuration data from serial ROM at reset the I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

•

DUART

— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

•

Enhanced local bus controller (eLBC)

— Multiplexed 32-bit address and data bus operating at up to 150-MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.

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