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AK8180D データシート(PDF) 5 Page - Asahi Kasei Microsystems |
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AK8180D データシート(HTML) 5 Page - Asahi Kasei Microsystems |
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5 / 12 page ![]() AK8180D MS1306-E-01 Oct-2011 - 5 - Power Supply Current <3.3V> VDD= 3.3V 5%, Ta: -40 to +85 ℃ Parameter Symbol Conditions Min Typ Max Unit Full operation (1) IDD1 CCLK0=250MHz CLK_SEL=L 95 120 mA Quiescent state (1)(2) IDD2 1.6 2.6 mA (1) The outputs have no loads. (2) All inputs are in default state by the internal pull up/down resisters. DC Characteristics <3.3V> All specifications at VDD=VDDA=VDDB=VDDC= 3.3V 5%, Ta: -40 to +85 ℃, unless otherwise noted Parameter Symbol Conditions MIN TYP MAX Unit High Level Input Voltage VIH LVCMOS 2.0 VDD+0.3 V Low Level Input Voltage VIL LVCMOS -0.3 0.8 V Peak-to-Peak Input Voltage Vpp LVPECL 250 mV Common Mode Range (1) Vcmr LCPECL 1.1 VDD-0.6 V Input Current (2) IL1 Vin=GND or VDD 200 μA High Level Output Voltage VOH IOH= -24mA (3) 2.4 V Low level Output Voltage VOL IOL= +24mA (3) IOL= +12mA 0.55 0.30 V Output Impedance 14-17 (1) Vcmr(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within t he Vcmr range and the input swing lies within the Vpp(DC) specification. (2) Input pull-up / pull down resistors influence input current. (3) The AK8180D is capable of driving 50 transmission lines of the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. (4) IDDQ is the DC current consumption of the device with all outputs open and the input in its default state or open. AC Characteristics <3.3V> (1) All specifications at VDD=VDDA=VDDB=VDDC= 3.3V 5%, Ta: -40 to +85 ℃, unless otherwise noted (continued on next page) Parameter Symbol Conditions MIN TYP MAX Unit Input Frequency fIN Pin: PCLKp/n 0 250 MHz Input Pulse Width tpwIN Pin: PCLKp/n 1.4 ns Peak-to-Peak Input Voltage Vpp Pin: PCLKp/n 500 1000 mV Common Mode Range (2) Vcmr Pin: PCLKp/n 1.3 VDD-0.8 Input Rise/Fall time (3) trIN,tfOUT Pin: PCLKp/n 0.8 to 2.0V 1.0 ns Output Frequency fOUT Pin: Q0-11 0 250 MHz Propagation Delay tPLH tPHL PCLK to any Q 1.3 2.2 3.55 ns Output Disable Time tPLZ,tPHZ 10 ns Output Enable Time tPZL,tPZH 10 ns Output-to-Output Skew tskPP Within one bank Any output, same output divider Any output, Any output divider 150 200 350 ps Device-to-Device Skew tskD 2.25 ns Output Pulse Skew (4) tskO 200 ps |
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