AK8180D datasheet(7/12 Pages) AKM

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AK8180D

MS1306-E-01

Oct-2011

- 7 -

AC Characteristics <2.5V> (1)

All specifications at VDD=VDDA=VDDB=VDDC= 2.5V

5%, Ta: -40 to +85

℃, unless otherwise noted

(1)

AC characteristics apply for parallel output termination of 50

 to VTT.

(2)

The AK8180D is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.

(3)

Violation of the 1.0 ns maximum input rise and fall tim e limit will affect the device propagation delay, device-to-device skew,

input pulse width, output duty cycle and maximum frequency specifications.

(4)

Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.

Output duty cycle is frequency dependent (= 0.5

 tskO x fout). For example at fout = 125 MHz the output duty

cycle limit is 50%

 2.5%.

AC Characteristics <mixed with 3.3V and 2.5V> (1)(2)

All specifications at VDD, VDDB= 3.3V

5%, VDDA, VDDC=2.5V5%, Ta: -40 to +85

℃, unless otherwise noted

(1)

AC characteristics apply for parallel output termination of 50

 to VTT.

(2)

For all other AC specifications, refer to 2.5V and 3.3V tables according to the supply voltage of the output bank .

(3)

Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.

Output duty cycle is frequency dependent (= 0.5

 tskO x fout). For example at fout = 125 MHz the output duty

cycle limit is 50%

 2.5%.

Parameter

Symbol

Conditions

MIN

TYP

MAX

Unit

Input Frequency

(2)

fIN

Pin: PCLKp/n

250

MHz

Input Pulse Width

tpwIN

Pin: PCLKp/n

1.4

Peak-to-Peak Input Voltage Vpp

Pin: PCLKp/n

500

1000

Common Mode Range

(2)

Vcmr

Pin: PCLKp/n

1.1

VDD-0.7

Input Rise/Fall time

(3)

trIN,tfOUT Pin: PCLKp/n

0.8 to 2.0V

1.0

Output Frequency

(2)

fOUT

DSELx = 0 x1 output

DSELx = 1 x1/2 output

250

125

MHz

Propagation Delay

tPLH

tPHL

PCLKp/n to any Q

1.4

2.4

4.4

Output Disable Time

tPLZ,tPHZ

Output Enable Time

tPZL,tPZH

Output-to-Output Skew

tskPP

Within one bank

Any output, same output divider

Any output, Any output divider

150

200

350

Device-to-Device Skew

tskD

3.0

Output Pulse Skew

(4)

tskO

200

Output Duty Cycle

DCOUT

DCREF= 50% x1 or 1/2 output

Output Rise/Fall Time

tr, tf

0.6 to 1.8V

0.1

1.0

Parameter

Symbol

Conditions

MIN

TYP

MAX

Unit

Propagation Delay

tPLH

、tPHL

PCLK to any Q

See 3.3V table

Output-to-Output Skew

tskPP

Within one bank

Any output, same output divider

Any output, Any output divider

150

250

350

Device-to-Device Skew

tskD

2.5

Output Pulse Skew

(3)

tskO

250

Output Duty Cycle

DCOUT

DCREF= 50% x1 or 1/2 output

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