Analog Integrated Circuit Device Data



Freescale Semiconductor

42

33813

5.3.8

SPI REGISTER DEFINITIONS

There are three basic SPI register types:

Configuration Registers - used to set the operating modes and parameters for the 33813 functional blocks. Each output can

be configured by setting the individual bits in the configuration register for that output according to the descriptions in the previous

functional descriptions for each particular output.

Control Registers - used to turn outputs on and off and set the PWM duty cycle for outputs that are used as PWM outputs. Also

used to set the temporary operating parameters for the watchdog timer and the VRS circuit.

Status Registers - used to annunciate faults and other values that the MCU may need to act upon. Each output and functional

block has a status register associated with it and the individual fault bits for each of the faults monitored are contained in these

registers. An “Any Fault” bit, bit 7, is the OR of all the individual fault bits in the register and indicates that one or more of the fault

bits is set. There is a system-wide “Any Fault” bit in the power supply and Any Fault Status register 13, (Bit 7) whose state is the

OR of all the other “Any Fault” bits in the other status registers. The MCU can monitor this system-wide Any Fault bit to discover

if any of the outputs has a fault condition present. Once the MCU detects the system-wide Any Fault bit =1, then it must

interrogate the all the other Status registers to determine the actual fault(s) that are present.

Once a fault bit in any status register is set, by the 33813 circuit, it can only be cleared by the MCU or by any of the reset actions

including a software reset.

Non-fault bits in the status register can be set and cleared by the 33813 circuit. All existing bits in the status register, bits not

marked as “x” can only be cleared by the MCU when the POST bit is zero (0). When the POST bit is one (1), the MCU can read

or write any existing bit in the status register. Non-existing bits, marked with an “x” in the table cannot be changed from the default

zero (0) value.

5.3.8.1

Existing and Non-existing Bits in the SPI Registers

Entries in the following SPI registers marked with an “x” are non-existent bits. They are set to zero (0) by default and cannot be

changed by reading or writing to them. They should be ignored when testing registers during POST.

System On/Off Indicators

One of the registers in the status register contains the On/Off status indication of the six LSDs and three pre-driver outputs (The

TACHOUT output is the only output not annunciated in this register). The output is consider to be On (1) whenever all of the

following conditions are true:

1. The output is commanded on via the Input pin or/and SPI bit, subject to the OR/AND logic condition selected.

2. There are no over-current (OC), short to battery (SB), or over-temperature (OT) faults present.

3. If PWM is enabled, the PWM control is set to a value greater than 0%.

4. There is no reset condition present. (OV, UV, WD, SW)

5. The 33813 is in the Normal state. (i.e. KEYSW =1)

Note: For ROUT2, the 33813 can be in either the Normal state or the Pre-shutdown state if the shutdown disable (SDD) bit is set

and PWREN=1.

If all of the five conditions above are true, the System On/Off bit for that output will be on (1).

If any of the five conditions above are false, the System On/Off bit for that output will be off (0).

5.3.8.2

Model Code and Revision Number

One status register is reserved for reporting the model code and revision of the 33813 circuits. The model code for the 33813 is

010. The revision code is the current version number for the circuit. This register is read-only.

5.3.9

SPI Command Summary

The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 7 separate commands

that are used to set the operational parameters of device. The operational parameters are stored internally in 8-bit registers. Write

commands write the data contained in the present SPI word whereas read commands have to wait until the next SPI command

is sent to read the data requested.