OR3LP26B datasheet(96/184 Pages) AGERE

部品番号	OR3LP26B

部品情報	Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

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メーカー	AGERE [Agere Systems]

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Master Read, Nonburst Transaction

Figure 30 (FPGA bus) and Figure 29 (PCI bus) show the timing of a single Quadword Master read. In Figure 30,

the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the

command and burst length on bus mwdata. On the next clock, the FPGA application provides the DWORD

address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn are deasserted. PCI bus

activity now begins as shown in Figure 29. Once data is transferred on the PCI bus and mr_emptyn is deasserted

high, the FPGA application asserts mrdataenn and two DWORDs of data are transferred on bus mrdata.

5-8849(F).a

Figure 29. Master Read Single (PCI Bus, 64-Bit)

ADRS

DATA

CMD

BEs

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

OR3LP26B データシート(PDF) 96 Page - Agere Systems