OR3LP26B datasheet(44/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Master Read, Nonburst Transaction

Figure 6 (FPGA bus) and Figure 7 (PCI bus) show the timing of a single Quadword Master read. In Figure 6, the

transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the

command, burst length, and lower DWORD address on bus datafmfpga. On the next clock, the FPGA application

provides the upper DWORD address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn

are deasserted. PCI bus activity now begins as shown in Figure 7. Once data is transferred on the PCI bus and

mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and one Quadword of data is trans-

ferred on bus datatofpga.

5-8833(F).a

Figure 6. Master Read Single (FPGA Bus, Dual-Port, Specified Burst Length, 64-Bit Address)

TN+1

TN+2

TN+3

CMD

BRST

ADRS

DATA

fclk

ma_fulln

mstatecntr

mcmd

datatofpga

maenn

mrdataenn

mrlastcycn

mr_emptyn

datafmfpga

mwlastcycn

mr_aemptyn

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