OR3LP26B datasheet(17/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

Arbitration Parking

The PCI Specification requires that all master agents

properly handle bus parking, which means that when

that agent receives an asserted gntn without the agent

having asserted reqn, the agent still must drive signal

par and buses AD and c_ben. The PCI core meets this

requirement.

Parity

The PCI core implements all required and optional fea-

tures, including the following:

Master generates parity on all addresses placed on

the bus.

Sending agent generates parity on all data placed on

the bus.

Target calculates parity on all addresses received

from the bus.

Receiving agent calculates parity on all data

received from the bus.

The detected parity error bit in the status register is

set whenever an agent calculates corrupted parity.

The signal perrn is generated whenever an agent

calculates corrupted parity and the parity error

response bit is set in the command register.

66 MHz Operation

The PCI core is fully compliant to PCI Specification

requirements at all clock rates up to 66 MHz. All

33 MHz requirements are also met.

Timing Budget

The PCI core’s timing budget is summarized in Table 5.

Note that the 66 MHz timing requirements only allow

5 ns for signal propagation (TPROP), as compared to

10 ns at 33 MHz. The effect of the reduction is to also

reduce the number of agents that the bus can support,

although the actual number is not specified in the PCI

Specification and is dependent on the design of the

hardware components. The four components of the

timing budget are TVAL (valid output delay), TPROP

(propagation time), TSU (input setup time), and TSKEW

(clock skew); of these, only TVAL and TSU are controlled

by the PCI component, and TPROP and TSKEW are sys-

tem parameters. Table 5 includes a third column (also

shown in the PCI Specification). This column indicates

the performance attainable if all 66 MHz requirements

are met except TPROP = 10 ns, which is the 33 MHz

value. In this case, the total budget increases from

15 ns (66 MHz) to 20 ns (50 MHz).

Table 5. Timing Budgets

64-Bit Addressing

The PCI core fully supports 64-bit addressing, whether

or not the PCI core is configured to utilize the 64-bit

data extension. When the PCI core is a 64-bit target

being addressed by 64-bit master, the PCI core will

decode the address one cycle faster so that dual-

address operation will have no performance impact;

see PCI Specification section 3.9 for details.

Section 3.9 of the PCI Specification also states that a

Master that supports 64-bit addressing must neverthe-

less generate requests utilizing a single address

instead of a dual address when the upper 32 bits are all

zeros. This shortens the request time by one cycle

when communicating with 32-bit Targets. It is the FPGA

application’s responsibility to ensure that this require-

ment is met.

FIFO Memories and Control

The OR3LP26B embedded core contains four FIFO

memories and supporting control logic. Two FIFOs are

for the master interface data and two for the target

interface data. These FIFOs are always configured to

operate in 64-bit mode and also carry byte enable bits

on a per-byte basis (e.g., the 64-bit FIFO actually car-

ries 64 bits of data and 8 byte enable bits for a total of

72 bits). During 32-bit transactions, the FPSC will pack

the data to fully utilize the memories. All FIFOs have

four flags: Full, Almost Full (Full-4), Empty, and Almost

Empty (Empty+4). (See Table 6.) The FPGA applica-

tion is provided with the Full/Empty signal and Almost

Full/Empty signal associated with the FPGA side of the

FIFO. In addition, the FPGA application is provided

with the PCI side's Full/Empty signal (but not the

Almost Full/Empty signal), to enable checking for oper-

ation completion. Clocking for the FPGA side of all

FIFOs is flexible, with options for different clocks for the

Master and Target FIFOs, sourced by the FPGA logic,

or by the PCI bus clock.

Timing Element 33 MHz 50 MHz 66 MHz

Unit

Cycle Time

30.0

20.0

15.0

Valid Output

Delay

11.0

7.5

6.0

Propagation

Time

10.0

6.5

5.0

Input Setup Time

7.0

4.5

3.0

Clock Skew

2.0

1.5

1.0

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