LAN9500AI datasheet(22/66 Pages) SMSC

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USB 2.0 to 10/100 Ethernet Controller

Datasheet

Revision 1.1 (04-18-13)

SMSC LAN950x Family

DATASHEET

PHY Interrupt

(Internal PHY

Mode)

nPHY_INT

In internal PHY mode, this pin can be configured

to output the internal PHY interrupt signal.

Note:

The internal PHY interrupt signal is

active-high.

PHY Interrupt

(External

PHY Mode)

nPHY_INT

(PU)

In external PHY mode, the active-low signal on

this pin is input from the external PHY and

indicates a PHY interrupt has occurred.

+3.3V Analog

Power Supply

VDD33A

Refer to the device reference schematic for

connection information.

Note:

Pin 7 is a no-connect (NC) for

LAN9500A/LAN9500Ai, but may be

connected to VDD33A for backward

compatibility with LAN9500/LAN9500i.

External PHY

Bias Resistor

EXRES

Used for the internal bias circuits. Connect to an

external resistor to ground.

For LAN9500A/LAN9500Ai use 12.0K, 1%.

For LAN9500/LAN9500i use 12.4K, 1%.

Ethernet PLL

Power Supply

VDDPLL

This pin must be connected to VDDCORE for

proper operation.

Refer to Chapter 4, "Power Connections," on

page 25 and the device reference schematic for

additional connection information.

Table 3.7 I/O Power Pins, Core Power Pins, and Ground Pad

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

+3.3V I/O

Power

VDD33IO

Refer to the device reference schematic for

connection information.

Digital Core

Power Supply

Output

VDDCORE

Refer to Chapter 4, "Power Connections," on

page 25 and the device reference schematic for

connection information.

Exposed

pad on

package

bottom

(Figure 3.1)

Ground

VSS

Common Ground

Table 3.6 Ethernet PHY Pins (continued)

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

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