LAN9500AI datasheet(9/66 Pages) SMSC

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USB 2.0 to 10/100 Ethernet Controller

Datasheet

SMSC LAN950x Family

Revision 1.1 (04-18-13)

DATASHEET

Chapter 2 Introduction

2.1

Block Diagram

2.1.1

Overview

The LAN950x is a high performance Hi-Speed USB 2.0 to 10/100 Ethernet controller. With applications

ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB to Ethernet

dongles, and test instrumentation, the device is a high performance and cost competitive USB to

Ethernet connectivity solution.

The LAN950x contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device

controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with a total

of 30 KB of internal packet buffering.

The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed

standard. The device implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.

The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is

compliant with the IEEE 802.3 and IEEE 802.3u standards. An external MII interface provides support

for an external Fast Ethernet PHY, HomePNA, and HomePlug functionality.

Multiple power management features are provided, including various low power modes and "Magic

Packet", "Wake On LAN", and "Link Status Change" wake events. These wake events can be

programmed to initiate a USB remote wakeup.

An internal EEPROM controller exists to load various USB configuration information and the device

MAC address. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.

Figure 2.1 System Diagram

TAP

Controller

EEPROM

Controller

USB 2.0

Device

Controller

SRAM

Ethernet

PHY

10/100

Ethernet

MAC

FIFO

Controller

USB

PHY

LAN950x

MII: To optional

external PHY

Ethernet

EEPROM

JTAG

USB

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