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データシートサーチシステム |
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OMAP3530ECBC72 データシート(PDF) 179 Page - Texas Instruments |
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OMAP3530ECBC72 データシート(HTML) 179 Page - Texas Instruments |
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179 / 264 page  6.4.2.3 Placement OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 6.4.2.2.3 PCB Stackup The minimum stackup required for routing the OMAP35x is a six layer stack as shown in Table 6-14. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint. Table 6-14. OMAP35x Minimum PCB Stack Up LAYER TYPE DESCRIPTION 1 Signal Top Routing Mostly Horizontal 2 Plane Ground 3 Plane Power 4 Signal Internal Routing 5 Plane Ground 6 Signal Bottom Routing Mostly Vertical Table 6-15. PCB Stack Up Specifications NO. PARAMETER MIN TYP MAX UNIT NOTES 1 PCB Routing/Plane Layers 6 2 Signal Routing Layers 3 3 Full ground layers under LPDDR routing region 2 4 Number of ground plane cuts allowed within LPDDR routing region 0 Number of ground reference planes required for each LPDDR routing 1 5 1 layer Number of layers between LPDDR routing layer and reference ground 0 6 0 plane 7 PCB Routing Feature Size 4 Mils 8 PCB Trace Width w 4 Mils 9 PCB BGA escape via pad size 18 Mils 10 PCB BGA escape via hole size 8 Mils 11 Device BGA Pad Size See Note(1) 12 LPDDR Device BGA Pad Size See Note(2) 13 Single Ended Impedance, ZO 50 75 Ω 14 Impedance Control Z-5 Z Z + 5 Ω See Note(3) (1) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size. (2) Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size. (3) Z is the nominal singled ended impedance selected for the PCB specified by item 12. Figure 6-19 shows the required placement for the OMAP35x device as well as the LPDDR devices. The dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second LPDDR device is omitted from the placement. Submit Documentation Feedback TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 179 |
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