MMPF0100NPEP datasheet(82/137 Pages) FREESCALE

部品番号	MMPF0100NPEP

部品情報	Four to six buck converters, depending on configuration

PDF	137 Pages

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メーカー	FREESCALE [Freescale Semiconductor, Inc]

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Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0100

Functional Block Requirements and Behaviors

Power Generation

6.4.6

LDO Regulators Description

This section describes the LDO regulators provided by the PF0100. All regulators use the main bandgap as reference. Refer to

Bias and References Block Description section for further information on the internal reference voltages.

A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However,

the lowest bias currents may be attained by forcing the part into its Low Power mode by setting the VGENxLPWR bit. The use

of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded.

When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when

RESETBMCU is low.

Figure 24. General LDO Block Diagram

VGENx

VINx

VGENx

CGENx

VGENxEN

VGENxLPWR

VREF

VGENx

Interface

Discharge

MMPF0100NPEP データシート(PDF) 82 Page - Freescale Semiconductor, Inc