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MMPF0100NPEP データシート(PDF) 86 Page - Freescale Semiconductor, Inc

部品番号 MMPF0100NPEP
部品情報  Four to six buck converters, depending on configuration
PDF  137 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMPF0100NPEP データシート(HTML) 86 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
86
Freescale Semiconductor
PF0100
Functional Block Requirements and Behaviors
Power Generation
For more detail information, Table 93 through Table 98 provide a description of all registers necessary to operate all six general
purpose LDO regulators.
Table 93. Register VGEN1CTL - ADDR 0x6C
Name
Bit #
R/W
Default
Description
VGEN1
3:0
R/W
0x80
Sets VGEN1 output voltage.
See Table 90 for all possible configurations.
VGEN1EN
4
0x00
Enables or Disables VGEN1 output
0 = OFF
1 = ON
VGEN1STBY
5
R/W
0x00
Set VGEN1 output state when in Standby. Refer
to Table 92.
VGEN1LPWR
6
R/W
0x00
Enable Low Power Mode for VGEN1. Refer to
Table 92.
UNUSED
7
0x00
UNUSED
Table 94. Register VGEN2CTL - ADDR 0x6D
Name
Bit #
R/W
Default
Description
VGEN2
3:0
R/W
0x80
Sets VGEN2 output voltage.
See Table 90 for all possible configurations.
VGEN2EN
4
0x00
Enables or Disables VGEN2 output
0 = OFF
1 = ON
VGEN2STBY
5
R/W
0x00
Set VGEN2 output state when in Standby. Refer
to Table 92.
VGEN2LPWR
6
R/W
0x00
Enable Low Power Mode for VGEN2. Refer to
Table 92.
UNUSED
7
0x00
UNUSED
Table 95. Register VGEN3CTL - ADDR 0x6E
Name
Bit #
R/W
Default
Description
VGEN3
3:0
R/W
0x80
Sets VGEN3 output voltage.
See Table 91 for all possible configurations.
VGEN3EN
4
0x00
Enables or Disables VGEN3 output
0 = OFF
1 = ON
VGEN3STBY
5
R/W
0x00
Set VGEN3 output state when in Standby. Refer
to Table 92.
VGEN3LPWR
6
R/W
0x00
Enable Low Power Mode for VGEN3. Refer to
Table 92.
UNUSED
7
0x00
UNUSED



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