MMPF0100NPEP datasheet(15/137 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

PF0100

General Description

Features

General Description

The PF0100 is the Power Management Integrated Circuit (PMIC) designed primarily for use with Freescale’s i.MX6 series of

application processors.

5.1

Features

This section summarizes the PF0100 features.

• Input voltage range to PMIC: 2.8 - 4.5 V

• Buck regulators

•

Four to six channel configurable

• SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V

• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V

•SW2, 2.0 A; 0.4 to 3.3 V

• SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V

• SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V

•SW4, 1.0 A; 0.4 to 3.3 V

• SW4, VTT mode provide DDR termination at 50% of SW3A

•

Dynamic voltage scaling

•

Modes: PWM, PFM, APS

•

Programmable output voltage

•

Programmable current limit

•

Programmable soft start

•

Programmable PWM switching frequency

•

Programmable OCP with fault interrupt

• Boost regulator

•

SWBST, 5.0 to 5.15 V, 0.6 A, OTG support

•

Modes: PFM and Auto

•

OCP fault interrupt

•LDOs

•

Six user programable LDO

• VGEN1, 0.80 to 1.55 V, 100 mA

• VGEN2, 0.80 to 1.55 V, 250 mA

• VGEN3, 1.8 to 3.3 V, 100 mA

• VGEN4, 1.8 to 3.3 V, 350 mA

• VGEN5, 1.8 to 3.3 V, 100 mA

• VGEN6, 1.8 to 3.3 V, 200 mA

•

Soft start

•

LDO/Switch supply

• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400

A

• DDR memory reference voltage

•

VREFDDR, 0.6 to 0.9 V, 10 mA

•16 MHz internal master clock

• OTP(One time programmable) memory for device configuration

•

User programmable start-up sequence and timing

• Battery backed memory including coin cell charger

•I2C interface

• User programmable Standby, Sleep, and Off modes

MMPF0100NPEP データシート(PDF) 15 Page - Freescale Semiconductor, Inc

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