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SL3ICS1002F7AF データシート(PDF) 23 Page - NXP Semiconductors

部品番号 SL3ICS1002F7AF
部品情報  UCODE G2XM and G2XL
PDF  51 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

SL3ICS1002F7AF データシート(HTML) 23 Page - NXP Semiconductors

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139037
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 9 October 2012
139037
23 of 51
NXP Semiconductors
SL3ICS1002/1202
UCODE G2XM and G2XL
14.1 G2X Memory
For the general memory layout according to the standard Section 17, Ref. 1, refer to
Figure 6.17. The tag memory is logically subdivided into four distinct banks.
In accordance to the standard Section 17, Ref. 1, section 6.3.2.1. The tag memory of the
SL3ICS1002 G2XM is organized in following 4 memory sections:
The logical address of all memory banks begin at zero (00h).
Table 12.
G2X memory sections
Name
Size
Bank
Reserved memory (32 bit ACCESS and 32 bit KILL password)
64 bit
00b
EPC (excluding 16 bit CRC-16 and 16 bit PC)
240 bit
01b
TID (including unique 32 bit serial number)
64 bit
10b
User memory (G2XM only)
512 bit
11b
Fig 5.
G2X TID memory structure
Class Identifier
Mask-Designer Identifier
Model Number
Serial Number
TID
31
0
11
0
11
07
0
00h
07h
08h
13h
14h
1Fh
20h
3Fh
6
0
4
0
14h
1Fh
18h
19h
Version Number
Sub Version Number
E2h
006h
00000001h to FFFFFFFFh
Whenever the 32 bit serial
is exceeded the sub version
is incremented by 1
3Fh
00h
Addresses
Addresses
Addresses
Bits
Bits
LS Byte
LSBit
LSBit
MSBit
MSBit
MS Byte
LSBit
LSBit
MSBit
MSBit
00000b
0000010b
Sub Version Nr
Version (Silicon) Nr
Model Nr.
Mask ID
UCode EPC G2XM
00000b
0000011b
003h
006h
UCode EPC G2XL
00000b
0000100b
004h
006h
002h



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