MPC8248VR datasheet(25/61 Pages) FREESCALE

25 / 61 page

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

AC Electrical Characteristics

This figure shows signal behavior in MEMC mode.

Figure 10. MEMC Mode Diagram

NOTE

Generally, all SoC bus and system output signals are driven from the rising

edge of the input clock (CLKin). Memory controller signals, however,

trigger on four points within a CLKin cycle. Each cycle is divided by four

internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and

T3 at the falling edge, of CLKin. However, the spacing of T2 and T4

depends on the PLL clock ratio selected, as shown in Table 14.

This table is a representation of the information in Table 14.

Figure 11. Internal Tick Spacing for Memory Controller Signals

Table 14. Tick Spacing for Memory Controller Signals

PLL Clock Ratio

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

1:2, 1:3, 1:4, 1:5, 1:6

1/4 CLKin

1/2 CLKin

3/4 CLKin

1:2.5

3/10 CLKin

1/2 CLKin

8/10 CLKin

1:3.5

4/14 CLKin

1/2 CLKin

11/14 CLKin

CLKin

V_CLK

Memory controller signals

sp34/sp30

CLKin

for 1:2.5

for 1:3.5

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

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