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MPC8248VR データシート(PDF) 35 Page - Freescale Semiconductor, Inc

部品番号 MPC8248VR
部品情報  PowerQUICC II Family Hardware Specifications
PDF  61 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8248VR データシート(HTML) 35 Page - Freescale Semiconductor, Inc

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MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
35
Clock Configuration Modes
1011_101
80.0
160.0
2.5
200.0 400.0
4.5
360.0 720.0
8
25.0
50.0
1101_000
50.0
100.0
2.5
125.0 250.0
3
150.0 300.0
5
25.0
50.0
1101_001
50.0
100.0
2.5
125.0 250.0
3.5
175.0 350.0
5
25.0
50.0
1101_010
50.0
100.0
2.5
125.0 250.0
4
200.0 400.0
5
25.0
50.0
1101_011
50.0
100.0
2.5
125.0 250.0
4.5
225.0 450.0
5
25.0
50.0
1101_100
50.0
100.0
2.5
125.0 250.0
5
250.0 500.0
5
25.0
50.0
1101_101
62.5
125.0
2
125.0 250.0
3
187.5 375.0
5
25.0
50.0
1101_110
62.5
125.0
2
125.0 250.0
4
250.0 500.0
5
25.0
50.0
1110_000
50.0
100.0
3
150.0 300.0
3.5
175.0 350.0
6
25.0
50.0
1110_001
50.0
100.0
3
150.0 300.0
4
200.0 400.0
6
25.0
50.0
1110_010
50.0
100.0
3
150.0 300.0
4.5
225.0 450.0
6
25.0
50.0
1110_011
50.0
100.0
3
150.0 300.0
5
250.0 500.0
6
25.0
50.0
1110_100
50.0
100.0
3
150.0 300.0
5.5
275.0 550.0
6
25.0
50.0
1100_000
Reserved
1100_001
Reserved
1100_010
Reserved
1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
2 PCI_MODCK determines the PCI clock frequency range. See Table 17 for higher range configurations.
3 MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
4 CPM multiplication factor = CPM clock/bus clock
5 CPU multiplication factor = Core PLL multiplication factor
Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1)1,2 (continued)
Mode3
Bus Clock
(MHz)
CPM
Multiplication
Factor4
CPM Clock
(MHz)
CPU
Multiplication
Factor5
CPU Clock
(MHz)
PCI
Division
Factor6
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3]
Low
High
Low
High
Low
High
Low
High



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