データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

MPC8248VR データシート(PDF) 20 Page - Freescale Semiconductor, Inc

部品番号 MPC8248VR
部品情報  PowerQUICC II Family Hardware Specifications
PDF  61 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8248VR データシート(HTML) 20 Page - Freescale Semiconductor, Inc

Back Button MPC8248VR Datasheet HTML 16Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 17Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 18Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 19Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 20Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 21Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 22Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 23Page - Freescale Semiconductor, Inc MPC8248VR Datasheet HTML 24Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 61 page
background image
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
20
Freescale Semiconductor
AC Electrical Characteristics
This figure shows the FCC external clock.
Figure 4. FCC External Clock Diagram
This figure shows the SCC/SMC/SPI/I2C external clock.
Figure 5. SCC/SMC/SPI/I2C External Clock Diagram
Serial ClKin
FCC input signals
FCC output signals
FCC output signals
Note: When GFMR[TCI] = 1
Note: When GFMR[TCI] = 0
sp16b
sp17b
sp36b/sp37b
sp36b/sp37b
Serial CLKin
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18b
sp19b
sp38b/sp39b
(See note)
(See note)
Note: There are four possible timing conditions for SPI:
1. Input sampled on the rising edge and output driven on the rising edge.
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge (shown).
4. Input sampled on the falling edge and output driven on the rising edge.
Note: There are two possible timing conditions for SCC/SMC/I2C:
1. Input sampled on the falling edge and output driven on the falling edge (shown).
2. Input sampled on the falling edge and output driven on the rising edge.
new CLKin



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com