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AM79C90PC データシート(PDF) 24 Page - Advanced Micro Devices |
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AM79C90PC データシート(HTML) 24 Page - Advanced Micro Devices |
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24 / 62 page ![]() AMD P R E L I M I N A R Y 24 Am79C90 Bit Name Description 15 PROM PROMISCUOUS mode. When PROM = 1, all incoming packets are accepted. 14:08 RES RESERVED. Read as zeroes. Write as zeroes. 07 EMBA Enable Modified Back-off Algorithm. When set (EMBA=1), enables the modified backoff algorithm. EMBA is cleared by activation of the RESET pin or setting the STOP bit. 06 INTL INTERNAL LOOPBACK is used with the LOOP bit to determine where the loopback is to be done. Internal loop- back allows the chip to receive its own transmitted packet. Since this represents full duplex operation, the packet size is limited to 8–32 bytes. Internal loopback in the C-LANCE is operational when the packets are addressed to the node itself. The C-LANCE will not receive any packets externally when it is in inter- nal loopback mode. EXTERNAL LOOPBACK allows the C-LANCE to transmit a packet through the SIA transceiver cable out to the Ethernet medium. It is used to determine the operability of all circuitry and connections be- tween the C-LANCE and the physi- cal medium. Multicast addressing in external loopback is valid only when DTCR = 1 (user needs to append the 4 bytes CRC). In external loopback, the C-LANCE also receives packets from other nodes. The FIFOs READ/WRITE pointers may misalign in the C-LANCE under heavy traffic. The packet could then be corrupted or not received. Therefore, the external loopback execution may need to be repeated. See specific discussion under “Loopback” in later section. INTL is only valid if LOOP = 1; other- wise, it is ignored. LOOP INTL LOOPBACK 0 X No loopback, normal 1 0 External 1 1 Internal 05 DRTY DISABLE RETRY. When DRTY = 1, the C-LANCE will attempt only one transmission of a packet. If there is a collision on the first transmission at- tempt, a Retry Error (RTRY) will be reported in Transmit Message De- scriptor 3 (TMD 3). Bit Name Description 04 COLL FORCE COLLISION. This bit allows the collision logic to be tested. The C-LANCE must be in internal loop- back mode for COLL to be valid. If COLL = 1, a collision will be forced during the subsequent transmission attempt. This will result in 16 total transmission attempts with a retry er- ror reported in TMD 3. 03 DTCR DISABLE TRANSMIT CRC. When DTCR = 0, the transmitter will gener- ate and append a CRC to the trans- mitted packet. When DTCR = 1, the CRC logic is allocated to the receiver and no CRC is generated and sent with the transmitted packet. The ADD_FCS bit (bit 13, TMD 1) can be used to override a DTCR=1 setting on a per packet basis. During loopback, DTCR = 0 will cause a CRC to be generated on the transmitted packet, but no CRC check will be done by the receiver since the CRC logic is shared and cannot generate and check CRC at the same time. The generated CRC will be written into memory with the data and can be checked by the host software. If DTCR = 1 during loopback, the host software must append a CRC value to the transmit data. The receiver will check the CRC on the received data and report any errors. 02 LOOP LOOPBACK allows the C-LANCE to operate in full duplex mode for test purposes. The packet size is limited to 8–32 bytes.The received packet can be up to 36 bytes (32 + 4 bytes CRC) when DTCR = 0. During loop- back, the runt packet filter is disabled because the maximum packet is forced to be smaller than the minimum size Ethernet packet (64 bytes). LOOP = 1 allows simultaneous transmission and reception for a message constrained to fit within the Transmit FIFO. The C-LANCE waits until the entire message is in the Transmit FIFO before serial trans- mission begins. The incoming data stream fills the Receive FIFO. Mov- ing the received message out of the Receive FIFO to memory does not begin until reception has ceased. |
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