AM79C90PC datasheet(25/62 Pages) AMD

25 / 62 page

P R E L I M I N A R Y

AMD

Am79C90

Bit

Name

Description

In loopback mode, transmit data

chaining is not possible. Receive

data chaining is possible if receive

buffers are 32 bytes long to allow

time for lookahead.

DTX

DISABLE

THE

TRANSMITTER

causes the C-LANCE to not access

the Transmitter Descriptor Ring, and

therefore, no transmissions are at-

tempted. DTX = 1 will clear the

TXON bit in CSR

0 when initialization

is complete.

DRX

DISABLE THE RECEIVER causes

the C-LANCE to reject all incoming

packets and not access the Receive

Descriptor Ring. DRX = 1 will clear

the RXON bit in the CSR

0 when in-

itialization is complete.

‘0’

1 0

PADR (47:01)

17881B-20

47:00

PADR

PHYSICAL ADDRESS is the unique

48-bit physical address assigned to

the C-LANCE. PADR (0) must be

zero.

Logical Address Filter

17881B-21

LADRF

63:00

LADRF

The

64-bit

mask

used

the

C-LANCE

logical

addresses.

The purpose of logical (or group or multicast) addresses

is to allow a group of nodes in a network to receive the

same message. Each node can maintain a list of multi-

cast addresses that it will respond to. The logical ad-

dress filter mechanism in the C-LANCE is a hardware

aide that reduces the average amount of host computer

time required to determine whether or not an incoming

packet with a multicast destination address should be

accepted.

The logical address filter hardware is an implementation

of a hash code searching technique commonly used by

software programmers. If the multicast bit of the desti-

nation address of an incoming packet is set, the

hardware maps this address into one of 64 categories

which correspond to 64 bits in the Logical Address Filter

packet depending on the state of the bit in the Logical

Address Filter Register which corresponds to the se-

lected category. For example, if the address maps into

category 24, and bit 24 of the logical address filter regis-

ter is set, the packet is accepted.

A node can be made a member of several groups by set-

ting the appropriate bits in the logical address filter

The details of the hardware mapping algorithm are as

follows:

If the first bit of an incoming address is a “1” [PADR (0)

=1], the address is deemed logical and is passed

through the logical address filter.

The logical address filter is a 64-bit mask composed of

four sixteen-bit registers, LADRF (63:00) in the initiali-

zation block, that is used to accept incoming Logical Ad-

dresses. The incoming address is sent through the CRC

circuit. After all 48 bits of the address have gone through

the CRC circuit, the high order 6 bits of the resultant

CRC (32-bit CRC) are strobed into a register. This regis-

ter is used to select one of the 64-bit positions in the

Logical Address Filter. If the selected filter bit is a “1,” the

address is accepted and the packet will be put in mem-

ory. The logical address filter only assures that there is a

possibility that the incoming logical address belongs to

the node. To determine if it belongs to the node, the in-

coming logical address that is stored in main memory is

compared by software to the list of logical addresses to

be accepted by this node.

The task of mapping a logical address to one of 64-bit

positions requires a simple computer program (see Ap-

pendix A) which uses the same CRC algorithm (used in

C-LANCE and defined per Ethernet) to calculate the

HASH (see Figure 7).

Driver software that manages a list of multicast ad-

dresses can work as follows. First the multicast address

list and the logical address filter must be initialized.

Some sort of management function such as the driver

initialization routine passes to the driver a list of ad-

dresses. For each address in the list the driver uses a

subroutine similar to the one listed in the appendix to set

the appropriate bit in a software copy of the logical ad-

dress filter register. When the complete list of addresses

has been processed, the register is loaded.

Later, when a packet is received, the driver first looks at

the Individual/Group bit of the destination address of the

packet to find out whether or not this is a multicast ad-

dress. If it is, the driver must search the multicast ad-

dress list to see if this address is in the list. If it is not in

the list, the packet is discarded.

AM79C90PC データシート(PDF) 25 Page - Advanced Micro Devices

AM79C90PC データシート(HTML) 25 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

データシートダウンロード