AM79C90PC datasheet(36/62 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C90

Serial Transmission

Serial transmission consists of sending an unbroken bit

stream from the TX output pin consisting of:

Preamble/SFD: 56 alternating ONES and ZEROES

terminating with the SFD byte (10101011).

Data: The serialized bit stream from the Transmit

FIFO Shifted out with LSB first.

CRC: The inverted 32-bit polynomial calculated

from the data, address, and type field. CRC is not

transmitted if:

— Transmission of the data field is truncated for

any reason.

— CLSN becomes asserted any time during

transmission.

— MODE <03> DTCR = 1 in a normal or loopback

transmission mode, and ADD_FCS=0 in the

transmit descriptor.

The Transmission is indicated at the output pin by the

assertion of TENA with the first bit of the preamble and

the negation of TENA after the last transmitted bit.

The C-LANCE starts transmitting the preamble when

the following are satisfied:

There is at least one byte of data to be transmitted

in the Transmit FIFO.

The interpacket delay has elapsed.

The backoff interval has elapsed, if doing a

retransmission.

Serial Reception

Serial reception consists of receiving an unbroken bit

stream on the RX input pin consisting of:

Preamble/SFD: Two ONES occurring a minimum

of 8 bit times after the assertion of RENA.

Destination Address: The 48 bits (6 bytes) follow-

ing the SFD.

Data: The serial bit stream following the Destina-

tion Address. The last 4 complete bytes of data are

the CRC. The Destination Address and the data

are framed into bytes and enter the Receive FIFO.

Source Address and Length field are part of the

data which are transparent to the C-LANCE.

Reception is indicated at the input pin by the assertion of

RENA and the presence of clock on RCLK while TENA

is inactive. The C-LANCE does not sample the received

data until about 800 ns after RENA goes high.

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