AM79C90PC datasheet(57/62 Pages) AMD

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Am79C90

Detailed Description of Enhancements

Process/Power Consumption

By using an advanced 0.8-micron CMOS process, the

CC speciﬁcation for the C-LANCE device is reduced to

50 mA maximum, compared to the 270 mA maximum

CC speciﬁcation for the LANCE device.

FIFOs

The C-LANCE device incorporates a dual FIFO (48

bytes Transmit, 64 bytes Receive) architecture to help

it compete for bandwidth on busy networks. The

LANCE device’s single 48-byte FIFO architecture and

its associated microcode has problems transmitting

packets out on busy networks. This problem is known

as the “Transmit Lockout Due to Receive” problem. It

occurs when minimum or near-minimum IFS trafﬁc is

continually received by the LANCE device and bus la-

tency is not “good” (“good” = latency < approximately

µs). In this situation, the LANCE device’s microcode

and bus interface is locked servicing receive packets,

and is not able to poll the pending transmit descriptor

(until the receive trafﬁc stops or does not pass address

match).

The C-LANCE device addresses this problem by in-

cluding dual FIFOs and microcode that is modiﬁed to

take advantage of the dual FIFOs. The microcode is

changed so that a transmit descriptor poll operation oc-

curs sometime early (exact time depends on bus laten-

cies and whether the receive buffer was owned before

the receive packet arrived) in the receive DMA opera-

tions for each packet. If the OWN bit in the TX descrip-

tor is found set, transmit FIFO loading DMA is

interleaved with the receive FIFO emptying DMA for the

packet being received. The transmit packet is then

ready to be transmitted immediately following the end

of the receive packet on the wire. The dual FIFOs and

microcode changes eliminate the possibility of transmit

activity being locked out due to high receive activity.

Interleaving the transmit DMA activity with receive

DMA activity at the beginning of a reception has the ef-

fect of increasing the bus latency for receive DMA op-

erations. To ensure that the C-LANCE device can

tolerate the same bus latency as the LANCE device,

the receive FIFO in the C-LANCE device is increased

to 64 bytes. The transmit FIFO in the C-LANCE device

holds 48 bytes.

Transmit Lockout Due to Receive

As discussed in item 2, the dual FIFO architecture and

modiﬁed microcode implemented in the C-LANCE de-

vice eliminates the possibility of Transmit Lockout Due

to Receive occurring.

Per-Packet FCS

In the LANCE device, addition of the Frame Check

Sequence (FCS or CRC) to each transmit packet is

controlled on a per-initialization basis. In other words,

when the DTCR (Disable Transmit CRC) bit is set in the

mode register at initialization, the only way that packets

can subsequently be transmitted with an FCS attached

is by re-initializing the device with the DTCR bit

cleared.

The C-LANCE device provides the capability to over-

ride the DTCR setting on a per-packet basis. If DTCR

was set in the mode register at initialization, the

ADD_FCS bit in the transmit descriptor can be used to

append FCS to transmitted packets on a per-packet

basis, overriding the DTCR setting. If DTCR is cleared

in the mode register, the ADD_FCS bit is a “don’t care.”

The ADD_FCS bit is located in bit 13 of TMD1 in the

C-LANCE device. This bit is RESERVED in the LANCE

device. Table B-2 below summarizes the operation of

the ADD_FCS bit. Note that the ADD_FCS bit is only

meaningful in the ﬁrst descriptor of a transmit buffer

chain (STP = 1).

Table B-2.

ADD_FCS Bit Operation

This feature should be compatible with existing imple-

mentations. Non-bridge nodes normally run with FCS

enabled (DTCR cleared). Bridges run with FCS dis-

abled. It is assumed that existing software in these

applications do not set bit 13 of TMD1, which was

previously RESERVED.

The ADD_FCS bit is also implemented as bit 13 of

TMD1 in the PCnet™-ISA (Am79C960) and operates

identically to the way in which it operates in the

C-LANCE device.

As a side note, this feature can be used by software to

distinguish the C-LANCE device from the LANCE

device. The LANCE device writes bit 13 of TMD1 to

zero when updating transmit status in the transmit

descriptor. The C-LANCE device will write this bit with

the value read, so if it is set to one it will be returned as

a one.

DTCR in

Mode Reg.

STP

ADD_FCS

FCS Added?

Yes

N/A

Yes

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