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AS3677

Datasheet - D e ta i l e d D e s c r i p t i o n

current source(s). Therefore the output signal does not show any PWM signal and therefore reduces the noise

in noise sensitive systems - especially if the connection to the LED used long wires.

Note:

For any current source, do not use DLS and the internal PWM generator (see PWM Generator on page 27) at

the same time.

Note:

If using dls_analog=1, the minimum PWM ratio is limited by the LED performance. If the analog current is

reduced too much, it might result in unevenness of the display backlight (as the LEDs are usually not specified

at very low current operation).

RGB1, RGB2 and RGB3 can only use ‘digital’ DLS - the register dls_analog does have no influence.

The analog processing of the DLS signal works as follows (dls_analog=1):

1. The input signal from pins DLS1 and DLS2 are feed into the digital filter. A logic ‘L’ is converted into ‘0.000’ and

a logic ‘H’ is converted into ‘1.000’.

2. The digital filter processes this signal. The filter itself is implemented as a 4th order low pass filter with fixed

coefficients. Its 3dB cut-off frequency is set to fDLS_FILTER.

3. The output signal (fixed comma binary 8 bit signal) is multiplied by the individual current setting.

4. From this 8 x 8 multiplication (16bit result), the 8 MSBs are used.

This value is converted with a current DAC into a current, which controls the LED.

8.4.8 Unused DLS Input Pins

The pins DLS1 and DLS2 should be connected to VSS if not used.

8.4.9 DLS Internal Processing

The internal processing is shown in Figure 25:

Table 75. DLS Input Parameters

Symbol

Parameter

Condition

Min

Typ

Max

Unit

fDLS

DLS input frequency

range

pins DLS1 and DLS2 if

used for DLS (any bit set:

curr1_on_dls,

curr2_on_dls or

curr6_on_dls); pin DLS1 if

used for RGB1, RGB2 and

RGB3 (only ‘digital’ DLS)

dls_analog=0

1000

kHz

dls_analog=1

300

1. For duty cycles >5%

25000

fDLS_FILTER

DLS internal filter 3dB

cutoff frequency

dls_analog=1, low pass filter 4th order

kHz

VIHDLS

High Level Input

Voltage

pins DLS1 and DLS2

1.38

VBAT

VILDLS

Low Level Input

Voltage

0.52

ILEAK

Input Leakage Current

to VBAT or VSS

-5

µA

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