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AS3677 データシート(PDF) 47 Page - ams AG |
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AS3677 データシート(HTML) 47 Page - ams AG |
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47 / 68 page ![]() www.austriamicrosystems.com/AS3677 1v3-1 46 - 67 AS3677 Datasheet - D e ta i l e d D e s c r i p t i o n 8.5.3 GPIO Registers VIHGPIO High Level Input Voltage pins ALS/GPIO1, GPIO2 and GPIO3 1.38 VANA V VILGPIO Low Level Input Voltage 0.52 V VHYS Hysteresis 0.1 V ILEAK Input Leakage Current to VANA or VSS -5 5 µA VOHGPIO High Level Output Voltage at Iout 0.8·VANA V VOLGPIO Low Level Output Voltage 0.2· VANA V VOLINT Low Level Output voltage Pin INT at 4mA 0.2 V IOUT Driving Capability VANA = 2.8V, gpio1_low_curr or gpio2_low_curr or gpio3_low_curr= 1 4 mA VANA = 2.8V, gpio1_low_curr or gpio2_low_curr or gpio3_low_curr= 0 10 1 CLOAD Capacitive Load 50 pF 1. Limited by LDO driving capability - see LDO on page 9 Table 80. GPIO output 2 Register Addr: 50h GPIO output 2 This register controls GPIO3 outputs. Bit Bit Name Default Access Description 0 gpio1_out 0R/W Writes a logic signal to pin ALS/GPIO1; this is independent of any other bit setting e.g., gpio1_mode Table 82. 1 gpio2_out 0R/W Writes a logic signal to pin GPIO2; this is independent of any other bit setting e.g., gpio2_mode Table 82 2 gpio3_out 0R/W Writes a logic signal to pin GPIO3; this is independent of any other bit setting e.g., gpio3_mode Table 83 Table 81. GPIO signal 2 Register Addr: 51h GPIO signal 2 This register controls GPIO3 outputs. Bit Bit Name Default Access Description 0 gpio1_in N/A R Reads a logic signal from pin ALS/GPIO1; this is independent of any other setting e.g.,Table 82 except gpio1_pulls=11 1 gpio2_ in N/A R Reads a logic signal from pin GPIO2; this is independent of any other setting e.g.,Table 82 except gpio2_pulls=11 2 gpio3_ in N/A R Reads a logic signal from pin GPIO3; this is independent of any other setting e.g.,Table 83 except gpio3_pulls=11 Table 79. GPIO and digital inputs DC Characteristics Symbol Parameter Condition Min Typ Max Unit |
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