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AS3677 データシート(PDF) 57 Page - ams AG

部品番号 AS3677
部品情報  Triple Channel Lighting Management Unit with DCDC step/up, ALS, 2xDLS(=DBC) and RGB Driver
PDF  68 Pages
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メーカー  AMSCO [ams AG]
ホームページ  http://www.ams.com
Logo AMSCO - ams AG

AS3677 データシート(HTML) 57 Page - ams AG

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AS3677
Datasheet - D e ta i l e d D e s c r i p t i o n
The clock line CLK is never held low by the AS3677 (as the AS3677 does not use clock stretching of the bus).
The AS3677 is compatible to the NXP two wire specification http://www.nxp.com/acrobat_download/literature/9398/
39340011.pdf, Version 2.1, January 2000 for standard and fast mode (no high speed mode).
8.10.1 Serial Interface Features
Fast Mode Capability (Maximum Clock Frequency is 400 kHz)
7-bit Addressing Mode
Write Formats
- Single-Byte Write
- Page-Write
Read Formats
- Current-Address Read
- Random-Read
- Sequential-Read
DATA Input Delay and CLK spike filtering by integrated RC components
8.10.2 Device Address Selection
The serial interface address of the AS3677 has the following address:
If ADR is connected to VSS: 80h – Write Commands, 81h – Read Commands
If ADR is connected to VBAT: 82h – Write Commands, 83h – Read Commands
Figure 31. Complete Serial Data Transfer
Serial Data Transfer Formats
Table 96. Serial Interface Voltages and Timings
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VIHI/F
High Level Input
Voltage
Pins DATA and CLK
1.38
VBAT
V
VILI/F
Low Level Input
Voltage
0.0
0.52
V
VHYSTI/F
Hysteresis
0.1
V
tRISE
Rise Time
0
1000
ns
tFALL
Fall Time
0
300
ns
VOL
Low Level Output
voltage
Pin DATA at 4mA
0.2
V
tCLK_FILTER
Spike Filter on CLK
100
ns
tDATA_FILTER
Spike Filter on DATA
300
ns
S
Start
Condition
Address R/W
ACK
Data
ACK
Data
ACK
Stop
Condition
P
DATA
CLK
1-7
8
9
1-7
89
1-7
8
9



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