DAC5687IPZP datasheet(48/79 Pages) TI

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B0168-01

PHSTR

PLLLOCK

MUX

CLK1

CLK1C

{PLLVDD,inv_plllock,dual_clk}

clk_in

Clock

Generator

CLK2

CLK2C

clk_out

FIFO

PHSTRSync

toNCO

PLL VCO

clk_nco

Phase

Accumulator

Reset

T0156-01

PHSTR

clk_in

clk_out

phstratFIFO

Output

clk_nco

Phase

ccumulator

eset

phase_accum

OnlyMustBe AssertedforOneclk_inPeriod

InputDelayLine+FIFODelay

13clk_ncoCycles

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

Figure 54. Logic Path for PHSTR Synchronization Signal to NCO

The serial interface includes a sync_nco bit in register SYNC_CNTL, which must be set for the PHSTR input

signal to initialize the phase accumulator.

The NCO uses a rising edge detector to perform the synchronous reset of the phase accumulator. Due to the

pipelined nature of the NCO, the latency from the phstr sync signal at the FIFO output to the instant the phase

accumulator is cleared is 13 fNCO clock cycles (fNCO = fDAC in X4 mode, fNCO = fDAC/2 in X2, X4L, and X8 modes).

In 2

× interpolation mode with the inverse sinc filter disabled, overall latency from PHSTR input to DAC output is

~100 input clock cycles.

Figure 55. NCO Phase Accumulator Reset Synchronization Timing

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