DAC5687IPZP datasheet(57/79 Pages) TI

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Power-Up Sequence

Sleep Mode

APPLICATION INFORMATION

Designing the PLL Loop Filter

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or

simultaneously with PLLVDD. AVDD, CLKVDD, and IOVDD can be powered simultaneously or in any order.

Within AVDD, the multiple AVDD pins should be powered simultaneously.

There are no specific requirements on the ramp rate for the supplies.

The DAC5687 features a power-down mode that turns off the output current and reduces the supply current to

less than 5 mA over the supply range of 3 V to 3.6 V and temperature range. The power-down mode is activated

by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal pulldown

circuit at node SLEEP ensures that the DAC5687 is enabled if the input is left disconnected. Power-up and

power-down activation times depend on the value of external capacitor at node EXTIO. For a nominal capacitor

value of 0.1

µF, power down takes less than 5 µs and approximately 3 ms to power back up.

Table 15. Optimum DAC5687 PLL Settings

fDAC (MHz)

pll_freq

pll_kv

pll_div(1:0)

fVCO/fDAC

Estimated GVCO (MHz/V)

25 to 28.125

380

28.125 to 46.25

250

46.25 to 60

300

60 to 61.875

130

61.875 to 65

225

65 to 92.5

250

92.5 to 120

300

120 to 123.75

130

123.75 to 130

225

130 to 185

250

185 to 240

300

240 to 247.5

130

247.5 to 260

225

260 to 370

250

370 to 480

300

480 to 495

130

495 to 520

225

The optimized DAC5687 PLL settings based on the VCO frequency MIN and MAX values (see the digital

specifications) as a function of fDAC are listed in Table 15. To minimize phase noise at a given fDAC, pll_freq,

pll_kv, and pll_div have been chosen so GVCO is minimized and within the MIN and MAX frequency for a given

setting.

For example, if fDAC = 245.76 MHz, pll_freq is set to 1, pll_kv is set to 0 and pll_div(1:0) is set to 01 (divide

by 2) to lock the VCO at 491.52 MHz.

The external loop filter components C1, C2, and R1 are set by the GVCO, N = fVCO/fDATA = fVCO ×

Interpolation/fDAC, the loop phase margin φd and the loop bandwidth ωd. Except for applications where abrupt

clock frequency changes require a fast PLL lock time, it is suggested that

d be set to at least 80 degrees for

stable locking and suppression of the phase-noise side lobes. Phase margins of 60 degrees or less can be

sensitive to board layout and decoupling details.

C1, C2, and R1 are then calculated by the following equations

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