CS4953 datasheet(13/44 Pages) CIRRUS

13 / 44 page

CS4952/53

DS223PP2

Digital to Analog Converters

The CS4952/3 provides four complete simulta-

neous 27 MHz DACs for analog video output: one

9-bit for S-video chrominance, one 9-bit for S-Vid-

eo luminance, and two 9-bit composite outputs.

Both S-Video DACs are designed for 37.5

Ω over-

all loads. The two composite 9-bit DACs are not

identical. One DAC is designed to drive 37.5

Ω de-

rived from a double terminated 75

Ω circuit. The

second 9-bit DAC is targeted for an on-board local

video connection where single point 75

Ω termina-

tion is sufficient i.e. Ch3/4 RF modulators, video

amps, muxes.

The DACs can be put into tri-state mode via host

addressable control register bits. Each of the four

DACs has its own separate DAC enable associated

with it. In the disable mode, the 9-bit DACs source

or sink zero current.

For lower power standby scenarios the CS4952/3

also provides power shut-off control for the DACs.

Each DAC has a separate DAC shut-off associated

with it.

Voltage Reference

The CS4952/3 is equipped with an on-board

1.235 V voltage reference generator used by the

Video DACs. For most requirements, the voltage

reference output pin can be connected to the volt-

age reference input pin along with a decoupling ca-

pacitor. Otherwise the voltage reference input may

be connected to an external voltage reference.

Current Reference

The DAC output current per bit is derived in the

current reference block. The current step is speci-

fied by the size of resistor place between the ISET

current reference pin and electrical ground. This

has been optimized for 10k

Ω (see “ISET” on

page 25 for more informmation on selecting the

proper ISET value).

Host Interface

The CS4952/3 provides a parallel 8-bit data inter-

face for overall configuration and control. The host

interface uses active low read and write strobes

along with an active low address enable signal to

provide microprocessor compatible read and write

cycles. Indirect host addressing to the CS4952/3 in-

ternal registers is accomplished via an internal ad-

dress register which is uniquely accessible via bus

write cycles with the host address enable signal as-

serted.

The CS4952/3 also provides an I2C compatible se-

rial interface for device configuration and control.

This port can operate in standard or fast (400 KHz)

modes. When in I2C mode, the parallel data inter-

face PDAT [7:0] pins may be used as a general pur-

pose I/O port controlled by the I

2C interface.

Closed Caption Services

The CS4952/3 supports the generation of NTSC

Closed Caption services. Line 21 and Line 284 cap-

tioning can be generated and enabled independent-

ly via a set of control registers. When enabled,

clock run-in, start bit, and data bytes are automati-

cally inserted at the appropriate video lines. A con-

venient interrupt interface simplifies the software

interface between the host processor and the

CS4952/3.

Control Registers

The control and configuration of the CS4952/3 is

primarily accomplished through the control regis-

ter block. All of the control registers are uniquely

addressable via the internal address register. The

control register bits are initialized during a chip re-

set.

See the detailed operation section of this data sheet

for all of the individual register bit allocations, bit

operational descriptions and initialization states.

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