CS4953 datasheet(30/44 Pages) CIRRUS

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CS4952/53

DS223PP2

Control Register 2

Address

0x02

CONTROL_2

Read/Write

Default Value = 00h

DAC Power Down Register

Address

0x04

DAC

Read/Write

Default Value = F0h

Bit Number

76543

Bit Name

RESERVED

SYNC_DLY

XTAL

SC_EN

Default00000

Bit

Mnemonic

Function

7:4

reserved

3Y_BW

Selects between 4.2 Mhz and 6 Mhz on-chip luminance low pass filters; default

value is zero which selects the 4.2 Mhz low pass filter option

SYNC_DLY

Delays expected timing of first active pixel input data relative to falling edge of

HSYNC from 245 27 MHz clock cycles to 246 for NTSC and from 265 to 266 for

PAL. Default State is SYNC_DLY=0 for no delay

XTAL

Crystal oscillator for subcarrier adjustment enable (1: enable)

SC_EN

Chroma burst disable (1: disable)

Bit Number

76543210

Bit Name

C_75_PD

C_37_PD

Y_PD

C_PD

C_75_EN

C_37_EN

Y_EN

C_EN

Default

11110000

Bit

Mnemonic

Function

C_75_PD

power down composite DAC with 75

Ω load (0: power up, 1: power down)

C_37_PD

power down composite DAC with 37.5

Ω load (0: power up, 1: power down)

Y_PD

power down luma s-video DAC (0: power up, 1: power down)

C_PD

power down chroma s-video DAC (0: power up, 1: power down)

C_75_EN

enable composite video DAC output for 75

Ω (0: tri-state, 1: enable)

C_37_EN

enable composite video DAC output for 37.5

Ω (0: tri-state, 1: enable)

Y_EN

enable s-video DAC for luma output (0: tri-state, 1: enable)

C_EN

enable s-video DAC for chroma output (0: tri-state, 1: enable)

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