MPC7457 datasheet(30/71 Pages) FREESCALE

30 / 71 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 10 shows the L3 bus timing diagrams for the MPC7457 interfaced to MSUG2 SRAMs.

Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs

5.2.4.3

L3 Bus AC Specifications for PB2 and Late Write SRAMs

When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in

Figure 11. These SRAMs are synchronous to the MPC7457; one L3_CLKn signal is output to each SRAM

to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed

L3_CLKn signal it received. The MPC7457 needs a copy of that delayed clock which launched the SRAM

read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and

L3_ECHO_CLK3 must be routed halfway to the SRAMs and returned to the MPC7457 inputs

L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2

are phase-aligned with the input clock received at the SRAMs. The MPC7457 will latch the incoming data

on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.

Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,

assuming the timing relationships of Figure 12 and the loading of Figure 8.

L3_ECHO_CLK[0,1,2,3]

L3 Data and Data

VM = Midpoint Voltage (GVDD/2)

Parity Inputs

L3_CLK[0,1]

ADDR, L3CNTL

tL3CHOV

tL3CHOX

L3DATA WRITE

tL3CHOZ

tL3CHDV

tL3CHDX

Outputs

Inputs

tL3CLDV

tL3CLDX

tL3CLDZ

tL3DVEH

tL3DXEL

tL3DVEL

tL3DXEH

Note: t

L3DVEH and tL3DVEL as drawn here are negative numbers, that is, input setup time is

time after the clock edge.

Note: t

L3CHDV and tL3CLDV as drawn here will be negative numbers, that is, output valid time will be

time before the clock edge.

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