WM8960 datasheet(69/92 Pages) WOLFSON

69 / 92 page

Production Data

WM8960

PD, August 2013, Rev 4.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

6:0

ROUT1VOL[6:0]

0000000

ROUT1 Volume

1111111 = +6dB

… 1dB steps down to

0110000 = -73dB

0101111 to 0000000 = Analogue MUTE

Analogue

Outputs

R4 (04h)

Clocking

(1)

8:6

ADCDIV[2:0]

000

ADC Sample rate divider (Also determines

ADCLRC in master mode)

000 = SYSCLK / (1.0 * 256)

001 = SYSCLK / (1.5 * 256)

010 = SYSCLK / (2 * 256)

011 = SYSCLK / (3 * 256)

100 = SYSCLK / (4 * 256)

101 = SYSCLK / (5.5 * 256)

110 = SYSCLK / (6 * 256)

111 = Reserved

Clocking and

Sample Rates

5:3

DACDIV[2:0]

000

DAC Sample rate divider (Also determines

DACLRC in master mode)

000 = SYSCLK / (1.0 * 256)

001 = SYSCLK / (1.5 * 256)

010 = SYSCLK / (2 * 256)

011 = SYSCLK / (3 * 256)

100 = SYSCLK / (4 * 256)

101 = SYSCLK / (5.5 * 256)

110 = SYSCLK / (6 * 256)

111 = Reserved

Clocking and

Sample Rates

2:1

SYSCLKDIV[1:0]

SYSCLK Pre-divider. Clock source (MCLK or

PLL output) will be divided by this value to

generate SYSCLK.

00 = Divide SYSCLK by 1

01 = Reserved

10 = Divide SYSCLK by 2

11 = Reserved

Clocking and

Sample Rates

CLKSEL

SYSCLK Selection

0 = SYSCLK derived from MCLK

1 = SYSCLK derived from PLL output

Clocking and

Sample Rates

R5 (05h)

ADC and

DAC

Control (1)

Reserved

DACDIV2

DAC 6dB Attenuate Enable

0 = Disabled (0dB)

1 = -6dB Enabled

Output Signal

Path

6:5

ADCPOL[1:0]

ADC polarity control:

00 = Polarity not inverted

01 = ADC L inverted

10 = ADC R inverted

11 = ADC L and R inverted

Analogue to

Digital Converter

Reserved

DACMU

DAC Digital Soft Mute

1 = Mute

0 = No mute (signal active)

Output Signal

Path

2:1

DEEMPH[1:0]

De-emphasis Control

11 = 48kHz sample rate

10 = 44.1kHz sample rate

01 = 32kHz sample rate

00 = No de-emphasis

Output Signal

Path

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