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WM8960 データシート(PDF) 20 Page - Wolfson Microelectronics plc |
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WM8960 データシート(HTML) 20 Page - Wolfson Microelectronics plc |
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20 / 92 page ![]() WM8960 Production Data w PD, August 2013, Rev 4.2 20 Figure 8 Microphone Input PGA Circuit The input PGAs and boost mixers are enabled by the AINL and AINR register bits. The microphone PGAs can be also be disabled independently of the boost mixer to save power, using LMIC and RMIC register bits. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R25 (19h) Power Management (1) 5 AINL 0 Left channel input PGA and boost stage enable 0 = PGA disabled, boost disabled 1 = PGA enabled (if LMIC = 1), boost enabled 4 AINR 0 Right channel input PGA and boost stage enable 0 = PGA disabled, boost disabled 1 = PGA enabled (if LMIC = 1), boost enabled R47 (2Fh) Power Management (3) 5 LMIC 0 Left channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if AINL = 1) 4 RMIC 0 Right channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if AINR = 1) Table 2 Input PGA and Boost Enable Register Settings The input PGAs can be configured as differential inputs, using LINPUT1/LINPUT2 or LINPUT1/LINPUT3, and RINPUT1/RINPUT2 or RINPUT1/RINPUT3. The input impedance to these non-inverting inputs is constant in this configuration. Differential configuration is controlled by LMP2, LMP3, RMP2 and RMP3 as shown in Table 3. When single-ended configuration is selected, the non-inverting input of the PGA is connected to VMID. |
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